Architecture for controlling dissipated power in a system-on-chip and related system

ABSTRACT

A system-on-chip (SoC) architecture includes a plurality of blocks, each including a power control module to selectively control the power dissipated by the bloc. For each block, a power register is provided to receive power control instructions to selectively control the respective power control module. The system also includes a power control unit for writing respective power control instructions into the power control registers of the blocks, whereby the power dissipated is controlled individually and independently for each block under the centralized control of the power control unit. For each block, a power status register is also provided to receive status information concerning power control within the respective block. The power control unit reads the status instructions from such power status registers.

FIELD OF THE INVENTION

[0001] The present invention relates to so-called Systems-on-Chip (SoC's) and is primarily concerned with controlling the power dissipated by various blocks or modules included in such a system.

BACKGROUND OF THE INVENTION

[0002] A wide variety of devices exist at present currently referred to as a System-on-Chip (SoC), such a designation being often adopted to designate in general devices integrating several digital blocks. Such an SoC has a structure of the type shown in FIG. 1, namely a structure including a plurality of rblocks M1, M2, . . . . Mn acting as “master” blocks as well as a plurality of blocks S1, S2, . . . . Sn acting as “slave” blocks. The blocks in question communicate through one or more buses. To simplify the description, just one bus designated BUS1—will be considered in the following. However, all the remarks made both in respect of the prior art and in respect of the invention apply identically to arrangements including a plurality of buses.

[0003] The “master” blocks are generally intended to control the SoC by controlling the “slave” blocks. For instance, one master block (e.g. master block M1) can be a CPU, while slave blocks S1, S2, . . . , Sn are quite often represented by peripheral units such as display units, interfaces, etc. Operation of the SoC 10, is synchronized by a clock signal, generated by a clock generator 12 to be distributed to the various blocks as indicated by lines 14. Again, a plurality of such clock generators may be included in a single SoC. In the following only one clock generator 12 and the respective clock signal will be considered for the sake of simplicity.

[0004] Technological development, especially in respect of integration of CMOS transistors, leads to an increasing level of integration of digital devices. As a result of this, increasingly complex and sophisticated circuits (including entire digital systems) can be integrated to a single device in the form of a SoC. A factor militating against that tendency is the amount of power dissipated in the form of heat by the device. For that reason, solutions are needed which enable a judicious reduction of the power dissipated by the device.

SUMMARY OF THE INVENTION

[0005] An object of the present invention is to provide an architecture that enables the power dissipated in an SoC to be effectively controlled and reduced.

[0006] In the arrangement of the invention the power dissipated by each individual IP (Intellectual Property) block is controlled independently with respect to the other IPs included in the same SoC via decentralized control functions adapted to be managed in a centralized manner. The advantages of the invention increase with the number of the digital blocks included in the SoC and with the diversity of such blocks. Nonetheless, the invention leads to advantageous results also in connection with very small systems.

[0007] The basic idea underlying the invention is to resort to a distributed control of dissipated power. Specifically, the architecture of the invention allows the dissipated power of the entire system to be controlled by individually controlling each IP in the system independently of the others by applying a central management function via a so-called Power Control Unit or PCU.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention will now be described, by way of example only, with reference to the enclosed figures of drawing, wherein:

[0009]FIG. 1 is a schematic block diagram of a conventional SoC; and

[0010]FIG. 2 is a schematic block diagram showing an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In FIG. 2, the same reference signs/numerals were used to designate parts/elements which are identical or equivalent to those already described in connection with FIG. 1.

[0012] The embodiment of the invention shown herein is based on the provision in the various blocks/modules, both of the master type (M1, M2, . . . , Mn) and of the slave type (S1, S2, Sn) of two registers designated PCR (Power Control Register) and PSR (Power Status Register), respectively. Preferably, such registers are also included in the clock generator block(s) 12. Registers PCR and PSR permit the status of the respective block to be controlled (activated/deactivated) and read individually for each block. This choice is primarily intended to permit the power dissipated to be controlled locally, that is by resorting to a distributed approach, while the power control policy is managed in a centralized manner.

[0013] Each block in SoC 10 is designed by using any of the techniques currently adopted for reducing the power dissipated, namely by “freezing” the respective clock signal (so-called “gated clock” approach), by reducing the clock frequency, etc. Such control action of the power dissipated may be effected—in a known manner—via respective signals that are generated locally via the PCR registers, which permits control of the power dissipated by each respective, individual digital block.

[0014] The enlarged view of slave block Sk shows, just by way of example, a respective power control unit 20 adapted to implement, via output line 20 a, a respective power control strategy e.g. of the “gated clock” or “clock division” type. Such as strategy is effected in conformity with power control signals provided by the corresponding PCR register over a line 20 b, as a function of the clock signal delivered over line 14. Similar arrangements are provided for all the other blocks included in SoC 10, thus permitting a respective power control strategy to be effected for each block distinctly and independently of any other block in the SoC.

[0015] The PSR registers, each of which is written by the corresponding block, enable the status of the block controlled to be read from outside. Reference 16 designates in FIG. 2 a so-called power control unit (PCU) which is connected via a bus line 18 with the PCR registers included in the various blocks of SoC 10. Power control unit 16 has the role of managing the power control “policy” of the whole SoC. This role can be performed in dependence of a variety of factors/parameters such as e.g.: the activity of bus BUS1, monitoring such activity by power control unit 16 is permitted by power control unit 16 being connected to such a bus; information on activity directly provided by the master and/or slave blocks; and information on activity read directly from the power state registers (PSR) of the master/slave blocks. Based on that information, power control unit 16 devises (in a manner known per se) a suitable power control policy which is effected by writing (via line 18) corresponding instructions in the power control registers PCR of the various master/slave blocks and clock generator 12 (which is preferably of the PLL generator type).

[0016] As an alternative to resorting to a dedicated bus such as bus 18 shown in FIG. 2, the control instructions in question can be sent from power control unit 16 to the various power control registers PCR via the main bus designated BUS1. In such a case, the power control information is written into registers PCR exactly as any other configuration information written into the registers of the various blocks of SoC 10. To advantage, the PCR registers can be written both by power control unit 16 and master blocks M1, M2, Mn. Similarly, registers PSR can be read both by power control unit 16 and by master blocks M1, M2, . . . , Mn.

[0017] The arrangement of the invention allows each and every block in the SoC to implement a respective, individual solution for reducing the dissipated power (e.g. clock gating, bus encoding, etc.) depending on the nature and function of the block itself. Thus, power dissipation may be controlled for each block independently from the other blocks while the power control strategy is supervised in centralized manner by power control unit 16 via power control registers PCR. Also, the various blocks can communicate with the power control unit 16 via power state registers PSR and also exchange information directly via bus 18 or BUS1.

[0018] The control process managed by power control unit 16 may thus vary to permit optimization of the results depending on the nature of SoC 10 and the various blocks to be controlled. In that way, the power control unit is in a position to use a simple, optimized architecture for system control.

[0019] The arrangement of the invention thus gives rise to a number of substantial advantages. First of all, the techniques of controlling reduction of dissipated power may be different and thus selectively chosen in an optimal manner for each block to be controlled. Secondly, each block can be controlled individually in terms of power reduction by suitably controlling the respective control signals, which enables a very precise control of the power dissipated. Finally, by resorting to central management of the power control strategy, operation of the whole system to be optimized by ensuring correct operation in data exchange between the blocks.

[0020] The basic idea of the invention can be extended and applied also at the design level, thus defining a standard based on the proposed architecture achieving full compatibility, in terms of controlling dissipated power, for any IP and/or CPU designed. This also applies to the possible re-use of IPs and in respect of interfacing with other IPs designed by resorting to the same principles. Of course, the basic principle of the invention remaining the same, the details and embodiments may wary with respect to what has been previously described by way of example only, without departing from the scope of the present invention as defined in the annexed claims. 

That which is claimed is:
 1. A system-on-chip (SoC) architecture including a plurality of blocks (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk), each block including a power control module (20) to selectively control the power dissipated by the block, characterized in that it includes a respective power control register (PCR) associated to each block of said plurality of blocks (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk), said power control register (PCR) to receive power control instructions to selectively control the power control module (20) of the associated block (12; M1, M2, . . . , Mn; S1, S2, Sk), and at least one power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks of said plurality (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk) whereby the power dissipated by said blocks is controlled individually and independently for each block of said plurality under the centralized control of said at least one power control unit (16).
 2. The architecture of claim 1, characterized in that it includes, for each block of said plurality (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk), a power status register (PSR) to receive status information concerning power control within the respective block and in that said at least one power control unit (16) is arranged to a read said status instructions from said power status registers (PSR) of the blocks of said plurality.
 3. The architecture of either of claims 1 or 2, characterized in that said at least one power control unit is a separate block (16) in the architecture.
 4. The architecture of either of claims 1 or 2, characterized in that said plurality of blocks includes at least one master block (M1, M2, . . . , Mn) configured for writing respective power control instructions into said power control registers (PCR) of the blocks of said plurality.
 5. The architecture of claim 2, characterized in that said plurality of blocks includes at least one master block (M1, M2, . . . , Mn) configured for reading said status instructions from said power status registers (PSR) of the blocks of said plurality.
 6. The architecture of any of the previous claims, including a main bus (BUS1) to exchange information between the blocks of said plurality (12; M1, M2, . . . , Mn; S1, S2, Sk) and in that said power control instructions are distributed from said at least one power control unit (16) to the power control registers (PCR) of the blocks of said plurality (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk) over said main bus (BUS1).
 7. The architecture of claim 2 and claim 5, characterized in that said status instructions are sent from the power status registers (PSR) of the blocks of said plurality towards said at least one power control unit (16) over said main bus (BUS1).
 8. The architecture of any of claims 1 to 5, characterized in that it includes a dedicated bus (18) for distributing said power control instructions from said at least one power control unit (16) towards the power control registers (PCR) of the blocks of said plurality (12; M1, M2, . . . , Mn; S1, S2, . . . , Sk).
 9. The architecture of claim 2 and claim 8, characterized in that said status instructions are sent from the power status registers (PSR) of the blocks of said plurality towards said at least one power control unit (16) over said dedicated bus (18).
 10. A system-on-chip (SOC) embodying the architecture of any of claims 1 to
 9. 